Advanced Microprocessor

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CONTENTS
1. 32-bit Microprocessor 80386
1. Introduction
2. Salient Features of Intel 80386 Microprocessor
3. Pins of 80386 Microprocessor
4. Architecture of 80386 Microprocessor
5. Memory Organisation
6. Register Organization of 80386
6.1 General Registers
6.2 Special Purpose Pointers
6.3 Segment Registers
6.4 Flags Register
6.5 Instruction Pointer
6.6 Segment Descriptor Cache Registers
6.7 Systems Address Registers
6.8 Control Registers of 80386
6.9 Debug Register (DR0 – DR7) and Test Registers (TR 6 and TR 7)
6.10 Debugging Support
6.11 TLB Testing
7. Real Addressing Mode of 80386
8. Protected Virtual Addressing Mode (PVAM) of 80386
9. Descriptor Tables in 80386
9.1 Global Descriptor Table (GDT)
9.2 Local Descriptor Table (LT)
9.3 Interrupt Descriptor Table (IDT)
10. Descriptors of 80386
10.1 Data Segment Descriptor
10.2 Code Segment Descriptor
10.3 System Segment Descriptor Formats
10.4 LDT Descriptors (S = 0, TYPE = 2)
10.5 TSS Descriptors (5 = 0, TYPE = 1, 3, 9, B)
10.6 GATE Descriptors (S = 0, TYPE = 4-7, C, F)
11. Selector Fields
12. Paging
12.1 Paging Concept
12.2 Enabling and Disabling Paging
12.3 Paging Mechanism
13. Virtual 8086 Mode
2. Introduction to Pentium Processor
1. Introduction to Pentium Processor
1.1 Salient Features of Pentium
2. System Architecture
2.1 Pentium Architecture
2.2 Superscalar Execution
2.3 Separate Code and Data Cache
2.4 Branch Prediction
2.5 Floating Point Unit (FPU)
2.6 Floating Point Pipeline Stages
2.7 Floating Point Exceptions
2.8 Special Pentium Registers
2.9 Built-In Self-Test (BIST)
2.10 Pentium Memory Management
3. Introduction to Pentium Pro-Processor
3.1 Special Pentium Pro-Features
3.2 Pentium Pro Micro Architecture
3.3 Dynamic Execution in Pentium Pro Processor
4. Introduction to Pentium-2 Processor
4.1 Features of Pentium-2 Processor
5. Pentium-III Processor
5.1 Features of Pentium III Processor
6. Introduction to Intel MMX
6.1 Features of MMX Pentium Processor
3. RISC Architecture
1. Introduction
2. CISC
3. History of RISC Processors
3.1 Hybrid Architecture-RISC and CISC Convergence
3.2 Advantages of RISC
3.3 Disadvantages of RISC
3.4 Basic Features of RISC Processors
3.5 Design Issues of RISC Processors
3.6 Sun Ultra SPARC
4. Interrupts of 8086 Microprocessor
1. Introduction to 8086 Interrupts
2. Types of Interrupts
2.1 Hardware Interrupts
2.2 Software Interrupts
3. Interrupt Processing Sequence
4. Interrupt Vector Table [IVT]
5. Special Interrupts
5.1 Divide-by-Zero Error-Type 0
5.2 Single-Step Interrupt-Type 1
5.3 Break Point Interrupt Instruction-Type 03
5.4 INTO - Interrupt on Overflow Instruction Type 04
5.5 BOUND Type 5
6. Priority of Interrupts
7. Introduction to MS-DOS
7.1 Organization of MS-DOS
7.2 Structure of MS-DOS
7.3 Loading of MS-DOS
8. Introduction to .COM Program
9. Introduction to .EXE Program
10. DOS and BOIS Interface
11. Interrupt Sources
12. DOS Interrupts
12.1 DOS Interrupt INT 21H
13. BIOS Interrupts
13.1 BIOS Interrupt INT 16H - Keyboard Services
14. Interrupt 13H: Disk l/O
15. BIOS Interrupt 17H: Printer

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